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INTEGRATED CIRCUITS
DATA SHEET
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* The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4016B gates Quadruple bilateral switches
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
Quadruple bilateral switches
DESCRIPTION The HEF4016B has four independent analogue switches (transmission gates). Each switch has two input/output terminals (Y/Z) and an active HIGH enable input (E). When E is connected to VDD a low impedance bidirectional path between Y and Z is established (ON condition). When E is connected to VSS the switch is disabled and a high
HEF4016B gates
impedance between Y and Z is established (OFF condition). Current through a switch will not cause additional VDD current provided the voltage at the terminals of the switch is maintained within the supply voltage range; VDD (VY, VZ) VSS. Inputs Y and Z are electrically equivalent terminals.
Fig.1 Functional diagram.
Fig.2 Pinning diagram.
PINNING E0 to E3 Y0 to Y3 Z0 to Z3 enable inputs input/output terminals input/output terminals HEF4016BP(N): 14-lead DIL; plastic (SOT27-1) HEF4016BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4016BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America APPLICATION INFORMATION Some examples of applications for the HEF4016B are: * Signal gating * Modulation * Demodulation * Chopper
Fig.3 Schematic diagram (one switch).
January 1995
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Philips Semiconductors
Product specification
Quadruple bilateral switches
RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Power dissipation per switch For other RATINGS see Family Specifications DC CHARACTERISTICS Tamb = 25 C; VSS = 0 V (unless otherwise specified) PARAMETER VDD V 5 ON resistance 10 15 5 ON resistance 10 15 5 ON resistance `' ON resistance between any two channels 10 15 5 10 15 RON RON RON RON SYMBOL TYP. 8000 230 115 140 65 50 170 95 75 200 15 10 MAX. - 690 350 425 195 145 515 285 220 - - - UNIT P max.
HEF4016B gates
100
mW
CONDITIONS En at VIH; Vis = 0 to VDD; see Fig.4
En at VIH; Vis = VSS; see Fig.4
En at VIH; Vis = VDD; see Fig.4
En at VIH; Vis = 0 to VDD; see Fig.4
PARAMETER
VDD V
Tamb (C) SYMBOL - IDD - - IIN - - IOZ - - - VIL - - 3,5 VIH 7,0 11,0 -40 - - - - - - - - - - 3,5 7,0 11,0 + 25 - - - - - - - - - - 3,5 7,0 11,0 + 85 UNIT A A A nA nA nA nA V V V V V V low-impedance between Y and Z (ON condition) see RON switch CONDITION
MIN. MAX. MIN. MAX. MIN. MAX. Quiescent device current Input leakage current at En OFF-state leakage current, any channel OFF En input voltage LOW En input voltage HIGH 5 10 15 15 5 10 15 5 10 15 5 10 15 1,0 2,0 4,0 - - - - 1,5 3,0 4,0 - - - 1,0 2,0 4,0 300 - - 200 1,5 3,0 4,0 - - - 7,5 15,0 30,0 1000 - - - 1,5 3,0 4,0 - - - VSS = 0; all valid input combinations; VI = VSS or VDD En at VSS or VDD En at VIL; Vis = VSS or VDD; Vos = VDD or VSS switch OFF; see Fig.9 for IOZ
January 1995
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Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4016B gates
Fig.4 Test set-up for measuring RON.
En > VIH Iis = 100 A VSS = 0 V
Fig.5 Typical RON as a function of input voltage.
January 1995
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Philips Semiconductors
Product specification
Quadruple bilateral switches
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; input transition times 20 ns VDD V Propagation delays Vis Vos HIGH to LOW 5 10 15 5 LOW to HIGH Output disable times En Vos HIGH 5 10 15 5 LOW Output enable times En Vos HIGH 5 10 15 5 LOW Distortion, sine-wave response Crosstalk between any two channels Crosstalk; enable input to output OFF-state feed-through ON-state frequency response 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 tPZL tPZH 40 20 15 40 20 15 - 0,08 0,04 - 1 - - 50 - - 1 - - 90 - 80 40 30 80 40 30 ns ns ns ns ns ns % % % MHz MHz MHz mV mV mV MHz MHz MHz MHz MHz MHz 10 15 tPLZ tPHZ 90 80 75 85 75 75 130 110 100 120 100 100 ns ns ns ns ns ns 10 15 tPLH tPHL 25 10 5 20 10 5 50 20 10 40 20 10 ns ns ns ns ns ns SYMBOL TYP. MAX.
HEF4016B gates
note 1
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note 7
January 1995
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Philips Semiconductors
Product specification
Quadruple bilateral switches
Notes Vis is the input voltage at a Y or Z terminal, whichever is assigned as input. Vos is the output voltage at a Y or Z terminal, whichever is assigned as output. 1. RL = 10 k to VSS; CL = 50 pF to VSS; En = VDD; Vis = VDD (square-wave); see Figs 6 and 10. 2. RL = 10 k; CL = 50 pF to VSS; En = VDD (square-wave); Vis = VDD and RL to VSS for tPHZ and tPZH; Vis = VSS and RL to VDD for tPLZ and tPZL; see Figs 6 and 11. 3. RL = 10 k; CL = 15 pF; En = VDD; Vis = 12VDD(p-p) (sine-wave, symmetrical about 12VDD); fis = 1 kHz; see Fig.7. 4. RL = 1 k; Vis = 12VDD(p-p) (sine-wave, symmetrical about 12VDD); V os (B) 20 log ------------------ = - 50 dB; E n (A) = V SS ; E n (B) = V DD ; see Fig. 8. V is (A) 5. RL = 10 k to VSS; CL = 15 pF to VSS; En = VDD (square-wave); crosstalk is Vos (peak value); see Fig.6. 6. RL = 1 k; CL = 5 pF; En = VSS; Vis = 12VDD(p-p) (sine-wave, symmetrical about 12VDD); V os 20 log -------- = - 50 dB; see Fig. 7. V is 7. RL = 1 k; CL = 5 pF; En = VDD; Vis = 12VDD(p-p) (sine-wave, symmetrical about 12VDD); V os 20 log -------- = - 3 dB; see Fig. 7. V is
HEF4016B gates
VDD V Dynamic power dissipation per package (P)(1) 5 10 15
TYPICAL FORMULA FOR P (W) 550 fi + (foCL) x VDD2 2 600 fi + (foCL) x VDD2 6 500 fi + (foCL) x VDD
2
where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V)
Note 1. All enable inputs switching.
January 1995
6
Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4016B gates
Fig.6
Fig.7
Fig.8
Fig.9
January 1995
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Philips Semiconductors
Product specification
Quadruple bilateral switches
HEF4016B gates
Fig.10 Waveforms showing propagation delays from Vis to Vos.
(1) Vis at VDD (2) Vis at VSS
Fig.11 Waveforms showing output disable and enable times.
January 1995
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